A sense amplifier (senseamp) is typically used to sense and refresh a bit value stored in a memory cell of a random access memory (RAM) such as, for example, a static random access memory (SRAM). The SRAM memory system is typically based on an array-structured memory architecture, which includes a plurality of sense amplifiers. The sense amplifier is a positive feedback device that pushes a readout voltage level to logic 1 (or high) or logic 0 (or low) with relatively high speed.
FIG. 1 is a block diagram of an embodiment of SRAM 100 having critical paths marked with thick shadow arrows. A read operation includes exemplary data paths A, B, C and D from global control 102 to memory array 108, and from global control 102 to read/write (RD/WR) circuit 112 and senseamp circuit 110. Such a read operation might have a long path delay. Thus, the read operation determines a read/write (RD/WR) operating frequency. The read path delay is primarily determined by the delay of global control 102 (e.g., an address register delay), the delay of row decoder 104, the access speed of SRAM cell 108 and the delay of senseamp circuit 110.
For a single data, bit input/output of SRAM 100, a single address of N+M bits is split into N row addresses and M column addresses. The row address is first decoded, so that one out of 2N word lines in the memory array (of size 2N×2M) is selected. SRAMs are usually built so that all cells in the same row are activated. Consequentially, all 2M bitline pairs form the columns leaving the memory array contain data. In a read operation, column decoder 106 selects one of these word line pairs based on the column address. Typically, a signal from each cell for example, cell 114, is sense-amplified by a sense amplifier in senseamp circuit 110, and stored in a data read buffer of RD/WR circuit 112. Differential bitlines, BL and BLB, emanating from cell 114 are provided to senseamp circuit 110, which pulls up a voltage differential between bitlines BL and BLB to a full level of the voltage differential. A signal is then gated out of the sense amplifier.
FIG. 2 is a schematic view of commonly used conventional implementation of sense amplifier 200. As shown in FIG. 2, sense amplifier 200 is a voltage latched based sense amplifier, which has a back to back inverter latch 210. As shown, internal nodes 202, 204 (INN, INP) of sense amplifier 200 are maintained at an unstable point and both are maintained at a drain supply voltage Vdd, rather than at a maximum gain point of Vdd/2. Sense amplifier 200 includes internal node INN 202, and INP 204, precharge circuit 206, load access elements 208 and 210, back to back inverters 212, output drivers 214, 216, and NMOS M5. Precharge circuit 206 includes PMOS transistors M6, M7 and M8 to precharge complimentary bitlines BL and BLB with a sense amplifier pre-charge signal (SAPRE). Load access element 208 includes capacitor CBL 220 and PMOS 222. PMOS 222 is configured as a transfer gate, allowing BL terminal to be connected to a storage node of capacitor CBL 220 under the control of SAPRE. One of the source/drain electrodes of PMOS 222 is connected, to the storage node of capacitor CBL 220, the other source/drain electrode of PMOS 222 is connected to BL, and the gate electrode of PMOS 222 is connected to SAPRE signal. Load access element 210 includes capacitor CBLB 224, PMOS 226 and current source Iin 228. PMOS 226 is configured as a transfer gate, allowing BLB terminal to be connected to a storage node of capacitor CBLB 224 wader the control of SAPRE. One of the source/drain electrodes of PMOS 226 is connected to the storage node of capacitor CBLB 224 and current source Iin 228, the other source/drain electrode of PMOS 226 is connected to BLB, and the gate electrode of PMOS 226 is connected to SAPRE signal. Current source Iin 228 is in parallel with capacitor CBLB 224 between the one of the source/drain electrodes of PMOS 226 and ground. Back to back inverters 212 includes NMOS transistors M1 and M2, and PMOS transistors M3 and M4 forming a cross-coupled latch. Output drivers 214, 216 each has one NMOS transistor and one PMOS transistor, which connect between the drain-to-drain, or power-supply, voltage, Vdd, and ground, to generate an inversion in the output of internal node 202 or 204 of sense amplifier 200. NMOS transistor M5 is connected at the common nodes of NMOS transistor M1 and M2 and driven by a sense amplifier enable signal (SAen). Internal node INN 202 and internal node INP 204 are each precharged to Vdd. When a read operation starts, depending on data to be read, either a voltage of BL or a voltage of the BLB starts to fall. If the voltage of BLB falls, the voltage of internal node INP 204 also starts to fall. As the voltage of internal node INP 204 falls to a level of an offset of sense amplifier 200, sense amplifier 200 is decoupled from BLB and the SAen signal is switched ON. This results in the cross-coupled latch in an unbalanced state. As such, a latching action of the cross-coupled latch automatically brings the voltage of internal node INP 204 to logic 0 and internal node INN 202 to Vdd, which is read at a memory output. Thus, internal node INN 202 and internal node INP 204 are kept at an unstable state point, instead of at a maximum gain point. Furthermore, a load of sense amplifier 200 also affects data carried by BL and BLB because of a direct connection of internal nodes 202, 204 and BL and BLB. Thus, sense amplifier 200 is generally not employed in designs with small bitlines.
In dual rail compilers the conventional sense amplifier also has limitations as the sense amplifier has to share a same voltage supply with the bitlines, increasing a consumption of the voltage supply of the array.